1. Field of the Invention
The present invention relates to a circuit and method for Analog-to-digital (A/D) conversion processing and a demodulation device which are used for a receiving device.
2. Description of Related Art
Conventionally in the field of data transmission, to address increase in transmission information amount, multiple-valued quadrature modulation has been employed in some cases which is represented by quadrature amplitude modulation (QAM) as a highly efficient modulation/demodulation method that allows transmitting a large amount of data without expanding a bandwidth.
QAM is performed by placing a symbol on each of lattice coordinate points on an IQ (in-phase and quadrature-phase) plane and assigning a predetermined bit count of digital code to each of the symbols. In a QAM modulator, digital data is converted in parallel for each predetermined bit count, and the converted parallel data is assigned to each of the symbols on the IQ plane. Values of the symbols in I, Q axes (I signal and Q signal) are subject to quadrature modulation to create a QAM-modulated wave to be transmitted.
On the other hand, a QAM demodulator determines the I, Q signals by quadrature detection using a carrier frequency of a reception signal. The QAM demodulator determines symbol positions on the IQ plane from the I, Q signals to obtain original data. Japanese unexamined patent publication No. 6-120997 (hereinafter referred to as document 1) discloses this kind of digital demodulation circuit technique. According to the proposal of the document 1, analog I, Q signals from a quadrature detection circuit are converted by two A/D converters to digital signals, respectively, from which signals, symbols are subsequently detected.
Incidentally, in recent years, a television receiver, etc., uses not only a composite signal but also I, Q signals as component signals for signal transmission from a tuner to a demodulation IC (integrated circuit), in some cases. That is, the tuner outputs an intermediate frequency (IF) signal as-is to the demodulation IC, or the tuner includes a quadrature detection circuit, outputs of which, i.e., I, Q signals, being outputted to the demodulation IC (Integrated Circuit).
In this case, a demodulation IC input stage requires a total of three A/D converters: one for high speed operation supporting the IF signal, and two for low speed operation supporting the I, Q signals. However, in an assumptive case of employing only one of the two systems of input signals, an unused A/D converter would turn out to be provided in the demodulation IC. Another problem is that the three A/D converters consume comparatively a large amount of electric power.
Note that similar problems as above also occur when converting three or more input signals to digital signals regardless of the kind of the input signals, for example when digitally converting each reception signal in diversity reception.